1. Field of the Invention
The present invention relates to lead frames and the manufacturing method thereof, and more particularly, to a lead frame in which the inner leads of the leads connect to electrodes of a semiconductor chip and the outer leads of the leads connect to electrodes of a printed circuit board or the like through protruding electrodes and the manufacturing method thereof.
2. Description of the Related Art
An example of a connection between a semiconductor chip and a printed circuit board or the like through an organic substrate having protruding electrodes such as solder balls is disclosed in U.S. Pat. No. 5,136,366. The structure of this conventional example will be described below by referring to its cross section shown in FIG. 1.
In FIG. 1, a semiconductor chip "b" is mounted on a surface of a multilayer organic wiring substrate "a" having about two to six layers and using an organic material. Wiring film "c" formed on the surface of the substrate "a" is connected to electrodes of the semiconductor chip "b" through connection wires "d" made of gold or the like.
Solder balls "e" formed on the opposite surface of the substrate "a" are electrically connected to the wiring film "c" via through holes. There is also shown solder resist film "f," sealing resin "g," and a printed circuit board "h."
In the conventional example shown in FIG. 1, the multilayer organic wiring substrate "a" with which the semiconductor chip "b" is mounted and resin-sealed on the main surface and the solder balls "e" serving as protruding electrodes are formed on the other surface is connected to the printed circuit board "h" with the solder balls "e."
Since electrodes of the semiconductor chip "b" are connected to the wiring film "c" on the multilayer organic wiring substrate "a" called BGA through the connection wires "d," made of gold or the like, parasitic resistance inevitably becomes large. In addition, a wire-bonding process is required, which requires time which cannot be ignored, thus being a factor for increasing cost.
Since the semiconductor chip "b" is mounted and resin-sealed on the main surface of the substrate "a," it is difficult to respond to an increasing demand for making semiconductor devices thinner.
There are also other drawbacks related to the multilayer organic wiring substrate "a." These are a very high manufacturing cost due to the complicated manufacturing process, a high defect rate which cannot be ignored due to its tendency to generate warps, and a probability of water invasion from the side faces of the substrate.